The present invention relates to a semiconductor device and, more particularly, to a nonvolatile semiconductor memory device of a charge-storage type.
In general, nonvolatile semiconductor memory devices of a charge-storage type are divided into two groups: floating-gate devices, such as the FAMOS (floating-gate avalanche-injection MOS, see: U.S. Pat. Nos. 3,660,819 and 3,984,822), and charge-trapping devices, such as the MNOS (metal silicon-nitride silicon-dioxide semiconductor) and the MAOS (metal alumina silicon-dioxide semiconductor).
In a floating-gate device, hot carriers generated due to avalanche breakdown are injected into a floating gate surrounded by an insulating material. On the other hand, in a charge-trapping device, carriers are injected into traps generated at the interface between two dissimilar insulating layers by using the tunnel effect. In these devices of an n-channel type, there are two states: a state in which electrons are accumulated in the floating-gate or in the traps so that a threshold voltage of the device is high, and a state in which electrons are driven out of the floating gate or the traps so that a threshold voltage of the device is low. In the devices of a p-channel type, there are also two states: a state in which holes are accumulated in the floating-gate or the traps, and a state in which holes are driven therefrom. The two different threshold voltages represent the two memory states "1" and "0".
In the conventional devices, in order to obtain long memory retentivity, i.e., good characteristics for storing information, the insulating layer between the substrate and the floating-gate (or the traps) is relatively thick, so that a special power supply at a high voltage is required to write information and erase it, in addition to the usual power supplies whose voltages are, for example, +12, +5 and -5 volts.
With the floating-gate devices, hot carriers, generated by avalanche breakdown which takes place in the vicinity of the drain junction, clear a potential barrier between the substrate and a first insulating layer and reach the floating gate. Therefore, if the potential barrier is diminished, a large number of hot carriers are injected into the floating-gate, which causes the control voltage to be decreased. At the same time, however, the potential barrier between the first insulating layer and the floating gate is also diminished, and accordingly a large number of the injected carriers are driven out of the floating gate through the first insulating layer to the substrate. This results in deterioration of the characteristics for storing information.
With the charge-trapping devices, the writing and erasing voltages can be decreased by reducing the thickness of a second insulating layer. However, when the thickness of the second insulating layer is reduced, the information storage characteristics are deteriorated and, in addition, undesired information is written during the read mode.